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Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration

Authors:

Wai-Kei MakAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 42, Pages 1 - 6

https://doi.org/10.1145/2897937.2898088

Published: 05 June 2016 Publication History

Abstract

In 10nm technology node, self-aligned double patterning (SA DP) and triple patterning lithography (TPL) allow us to achieve minimum wiring pitch of around 45nm. While metal layers can be printed by SADP, via layer manufacturing requires TPL to maintain design rules. SADP-aware detailed routing is proposed to ensure decomposability of metal layer patterns. However, its routing solution does not automatically guarantee TPL decomposable via layers. Vias have an inherently low reliability and via failure causes a great yield loss. Double via insertion (DVI) is an effective means to increase yield by reducing via failures. With the restriction of SADP design rules and consideration of TPL decomposability for via layers, DVI becomes a more challenging problem. In this paper, we consider DVI and via layer TPL manufacturability simultaneously in SADP-aware detailed routing. The experimental results demonstrate our router can obtain 100% routability and TPL decomposable via layers with reduced dead via count.

References

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Cited By

Ding YChu CMak W(2018)Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266037:3(657-668)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2712660
Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Cited By

Ding YChu CMak W(2018)Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266037:3(657-668)Online publication date: Mar-2018
https://doi.org/10.1109/TCAD.2017.2712660
Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478

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