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MicroFix: Using timing interpolation and delay sensors for power reduction

Authors:

Xiaowei LiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16, Issue 2

Article No.: 16, Pages 1 - 21

https://doi.org/10.1145/1929943.1929948

Published: 07 April 2011 Publication History

Abstract

Traditional DVFS schemes are oblivious to fine-grained adaptability resulting from path-grained timing imbalance. With the awareness of such fine-grained adaptability, better power-performance efficiency can be obtained. We propose a new scheme, MicroFix, to exploit such fine-grained adaptability. We first show the potential resulted from the path-grained timing imbalance and then present a new technique, Timing Interpolation, to reap the fine-grained adaptability for power reduction. Moreover, to eliminate the conservative margins of traditional DVFS, unlike the previous approaches such as Razor that reactively handle the delay errors (induced by aggressively scaled voltage/frequcncy) by enabling error detection and recovery, we propose a proactive approach by error prediction, thereby obviate the high-cost recovery routines. MicroFix was evaluated based on ISCAS89 benchmarks and the floating-point unit adopted by OpenSPARC T1 processor. Compared to ideal traditional DVFS schemes, the experimental results show that for most of the evaluated circuits, MicroFix can help saving up to 20% power consumption without compromising with frequency, at the expense of less than 5% area overhead. Compared to nonideal DVFS schemes (with 10% voltage margin), the power reduction can even reach up to 38% on average.

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Cited By

(2018)Single-layer obstacle-aware routing for substrate interconnectionsIntegration, the VLSI Journal10.1016/j.vlsi.2015.04.00151:C(1-9)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2015.04.001
Yan GLi X(2011)Online timing variation tolerance for digital integrated circuits2011 IEEE International Test Conference10.1109/TEST.2011.6139136(1-10)Online publication date: Sep-2011
https://doi.org/10.1109/TEST.2011.6139136

Index Terms

MicroFix: Using timing interpolation and delay sensors for power reduction
1. Hardware
  1. Integrated circuits

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 16, Issue 2

March 2011

180 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1929943

Issue’s Table of Contents

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 April 2011

Accepted: 01 December 2010

Revised: 01 December 2010

Received: 01 March 2010

Published in TODAES Volume 16, Issue 2

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Cited By

(2018)Single-layer obstacle-aware routing for substrate interconnectionsIntegration, the VLSI Journal10.1016/j.vlsi.2015.04.00151:C(1-9)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2015.04.001
Yan GLi X(2011)Online timing variation tolerance for digital integrated circuits2011 IEEE International Test Conference10.1109/TEST.2011.6139136(1-10)Online publication date: Sep-2011
https://doi.org/10.1109/TEST.2011.6139136

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