A methodology to improve yield in analog circuits by using geometric programming
Authors: 
Jorge Johanny Sáenz Noval, Elkim Felipe Roa Fuentes, Armando Ayala Pabón, Wilhelmus Van NoijeAuthors Info & Claims
Pages 140 - 145
Abstract
A CAD methodology to design analog circuits via geometric programming (GP) involving manufacturing issues is proposed. A functional approach by sensitivity analysis from dimensional variables is used to obtain the design space. A mismatch analysis using the Pelgrom's model defines the minimum area to ensure parametric yield requirements. With the information on the design space and minimum area, performance and yield are optimized with a new strategy called best-effort. This methodology is validated through the design of a sub-threshold voltage reference [1]. In this work a 3.25 ppm/C temperature coefficient is obtained with a deviation nine times lower but occupying the same area than the one using the GP strategy without manufacturing issues. Further, it is shown how an appropriate sizing can improve the yield up to 24%.
References
[1]
J. Mateus, E. Roa, H. Hernandez, and W. Van Noije, A 2.7ua sub1-v voltage reference," in SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design. New York, NY, USA: ACM, 2008, pp. 81--84.
[2]
N. Jakatdar, DFM: What, Why, When & How," Solid State Technology and Devices Seminar EECS 298--12, UC at Berkeley, February 2007.
[3]
S. Director, Optimization of parametric yield," in Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on, nov 1991, pp. 1--18.
[4]
M. Pelgrom, A. Duinmaijer, and A. Welbers, Yield Optimization of Analog IC's Using Two-Step Analytic Modeling Methods," Solid-State Circuits, IEEE Journal of, vol. 28, no. 7, pp. 778{783, July 1993.
[5]
B. Gregoire, Optimum area allocation for minimum mismatch {IC device area optimization}," in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, oct. 2004, pp. 643--646.
[6]
K. Low and S. Director, A new methodology for the design centering of IC fabrication processes," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 10, no. 7, pp. 895--903, Jul 1991.
[7]
A. Seifi, K. Ponnambalam, and J. Vlach, A unified approach to statistical design centering of integrated circuits with correlated parameters," Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 46, no. 1, pp. 190--196, Jan 1999.
[8]
J. Oliveros, D. Cabrera, E. Roa, and W. Van Noije, An improved and automated design tool for the optimization of CMOS OTAs using geometric programming," in SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design. New York, NY, USA: ACM, 2008, pp. 146--151.
[9]
M. Pelgrom, A. Duinmaijer, and A. Welbers, Matching properties of MOS transistors," Solid-State Circuits, IEEE Journal of, vol. 24, no. 5, pp. 1433--1439, Oct 1989.
[10]
S. Boyd and L. Vandenberghe, Convex Optimization, 1st ed. Cambridge University Press, 2004.
[11]
M. Grant and S. Boyd, CVX: Matlab software for disciplined convex programming," Internet, February 2009, build 711. {Internet}. Visite: http://stanford.edu/ boyd/cvx
[12]
P. Drennan and C. McAndrew, Understanding MOSFET mismatch for analog design," Solid-State Circuits, IEEE Journal of, vol. 38, no. 3, pp. 450--456, Mar 2003.
[13]
S.-C. Wong, K.-H. Pan, and D.-J. Ma, A CMOS mismatch model and scaling e ects," Electron Device Letters, IEEE, vol. 18, no. 6, pp. 261--263, jun 1997.
Index Terms
- A methodology to improve yield in analog circuits by using geometric programming
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Published In
September 2010
228 pages
ISBN:9781450301527
DOI:10.1145/1854153
- General Chair:
- João Antonio Martino,
- Program Chairs:
- Guido Araújo,
- Alex Orailoglu,
- Publications Chair:
- Felipe Klein
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Published: 06 September 2010
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