More Web Proxy on the site http://driver.im/

Article

A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations

Authors:

Songqing Zhang,

Kaustav BanerjeeAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 156 - 161

https://doi.org/10.1145/1013235.1013278

Published: 09 August 2004 Publication History

Abstract

This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.

References

[1]

S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, "Parameter variations and impact on circuits and microarchitecture," DAC, 2003, pp. 338--342.

Digital Library

[2]

S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, pp. 23--29, Jul-Aug 1999.

Digital Library

[3]

K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol. 37, pp. 183--190, Feb. 2002.

[4]

H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, "Full chip leakage estimation considering power supply and temperature variations," ISLPED, 2003, pp. 78--83.

Digital Library

[5]

R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical analysis of subthreshold leakage current for VLSI Circuits," IEEE Trans. on VLSI Systems, vol. 12, no.2, pp. 131--139, 2004.

Digital Library

[6]

S. Mukhopadhyay and K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," ISLPED, 2003, pp. 172--175.

Digital Library

[7]

S. Narendra, V. De, S. Borkar, D. Antoniadis and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18µm CMOS," ISLPED, 2002, pp. 19--23.

Digital Library

[8]

Srivastava, R. Bai, D. Blaauw and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," ISLPED, 2002, pp. 64--67.

Digital Library

[9]

Y. S. Lin, C. C. Wu, C. S. Chang, R. P. Yang, W. M. Chen, J. J. Liaw, and C. H. Diaz, "Leakage scaling in deep submicron CMOS for SoC," IEEE Trans. Electron Devices, vol. 49, pp. 1034--1041, Jun. 2002.

[10]

Intl. Technology. Roadmap for Semiconductors (ITRS): 2003:http://public.itrs.net/

[11]

K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. of the IEEE, vol. 91, no. 2, pp. 305--327, Feb, 2003.

[12]

S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling," DAC, 2003, pp. 169--174.

Digital Library

[13]

Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ. Press, 1998.

Digital Library

[14]

K. Banerjee, S. C. Lin, A. Keshavarzi, S. Narendra, and V. De, "A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management", IEDM, 2003, pp. 887--890.

[15]

J. Zhang and M. Styblinski, Yield and Variability Optimization of Integrated Circuits, Kluwer Academic Publishers, Boston, 1995.

[16]

BSIM3 manual: http://www-device.eecs.berkeley.edu/~bsim3/ftpv323/Mod_doc/BSIM3v323_manu.tar

[17]

http://www-device.eecs.berkeley.edu/~ptm/mosfet.html

Cited By

Sun JLysecky RShankar KKodi ALouri ARoveda J(2014)Workload assignment considering NBTI degradation in multicore systemsACM Journal on Emerging Technologies in Computing Systems10.1145/253912410:1(1-22)Online publication date: 13-Jan-2014
https://dl.acm.org/doi/10.1145/2539124
Harish BBhat N(2012)Performance and Variability Trade-off With Gate-to-Source/Drain Overlap LengthIETE Journal of Research10.4103/0377-2063.9618058:2(130)Online publication date: 2012
https://doi.org/10.4103/0377-2063.96180
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Show More Cited By

Index Terms

A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations
1. Hardware
  1. Very large scale integration design

Recommendations

Analysis and verification of power grids considering process-induced leakage-current variations

The ongoing trends in technology scaling imply a reduction in the transistor threshold voltage (V_th). With smaller feature lengths and smaller parameters, variability becomes increasingly important, for ignoring it may lead to chip failure and assuming ...
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS
DAC '06: Proceedings of the 43rd annual Design Automation Conference

Double-gate CMOS is projected to replace classical bulk and SOI technologies around the 32nm node. Predicting the impact of process variations on yield for these novel devices is necessary at an early stage of the design cycle, to enable optimal ...
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era
DAC '04: Proceedings of the 41st annual Design Automation Conference

Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (V_dd) and threshold (V_th) ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 August 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISLPED04

Sponsor:

ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

42
Total Citations
View Citations
270
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 14 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Sun JLysecky RShankar KKodi ALouri ARoveda J(2014)Workload assignment considering NBTI degradation in multicore systemsACM Journal on Emerging Technologies in Computing Systems10.1145/253912410:1(1-22)Online publication date: 13-Jan-2014
https://dl.acm.org/doi/10.1145/2539124
Harish BBhat N(2012)Performance and Variability Trade-off With Gate-to-Source/Drain Overlap LengthIETE Journal of Research10.4103/0377-2063.9618058:2(130)Online publication date: 2012
https://doi.org/10.4103/0377-2063.96180
Cheng LXu WGong FLin YWong HHe L(2012)Statistical Timing and Power Optimization of Architecture and Device for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2209285.22092885:2(1-19)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1145/2209285.2209288
Haghdad KAnis M(2012)Power yield analysis under process and temperature variationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216353520:10(1794-1803)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2163535
Nomani MAnis MKoley G(2010)Statistical Approach for Yield Optimization for Minimum Energy Operation in Subthreshold Circuits Considering Variability IssuesIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2009.203918423:1(77-86)Online publication date: Feb-2010
https://doi.org/10.1109/TSM.2009.2039184
Ghosh SRoy K(2010)Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale EraProceedings of the IEEE10.1109/JPROC.2010.205723098:10(1718-1751)Online publication date: Oct-2010
https://doi.org/10.1109/JPROC.2010.2057230
Mozaffari SAfzali-Kusha A(2010)Statistical model for subthreshold current considering process variations2nd Asia Symposium on Quality Electronic Design (ASQED)10.1109/ASQED.2010.5548311(356-360)Online publication date: Aug-2010
https://doi.org/10.1109/ASQED.2010.5548311
Ghosh S(2010)Effect of Variations and Variation Tolerance in Logic CircuitsLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_3(83-108)Online publication date: 25-Oct-2010
https://doi.org/10.1007/978-1-4419-7418-1_3
Kim NSeomun JSinkar ALee JHan TChoi KShin YHenkel JKeshavarzi AChang NGhani T(2009)Frequency and yield optimization using power gates in power-constrained designsProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594263(121-126)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594263
Heloue KAzizi NNajm F(2009)Full-chip model for leakage-current estimation considering within-die correlationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201654628:6(874-887)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2016546
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents