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Article

Coverage directed test generation for functional verification using bayesian networks

Authors:

Avi ZivAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 286 - 291

https://doi.org/10.1145/775832.775907

Published: 02 June 2003 Publication History

Abstract

Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or dynamic verification), by providing a new approach for Coverage Directed Test Generation (CDG). This approach is based on Bayesian networks and computer learning techniques. It provides an efficient way for closing a feedback loop from the coverage domain back to a generator that produces new stimuli to the tested design. In this paper, we show how to apply Bayesian networks to the CDG problem. Applying Bayesian networks to the CDG framework has been tested in several experiments, exhibiting encouraging results and indicating that the suggested approach can be used to achieve CDG goals.

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Cited By

Cheng SJin PGuo QDu ZZhang RHu XZhao YHao YGuan XHan HZhao ZLiu XZhang XChu YMao WChen TChen YLarson K(2024)Automated CPU design by learning from input-output examplesProceedings of the Thirty-Third International Joint Conference on Artificial Intelligence10.24963/ijcai.2024/425(3843-3853)Online publication date: 3-Aug-2024
https://dl.acm.org/doi/10.24963/ijcai.2024/425
Xiao CDeng YYang ZChen RWang HZhao JDai HWang LTang YXu W(2024)LLM-based Processor Verification: A Case Study for Neuromorphic Processor2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546707(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546707
Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
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Index Terms

Coverage directed test generation for functional verification using bayesian networks
1. Hardware
  1. Hardware validation
    1. Functional verification

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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DAC03

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SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Cited By

Cheng SJin PGuo QDu ZZhang RHu XZhao YHao YGuan XHan HZhao ZLiu XZhang XChu YMao WChen TChen YLarson K(2024)Automated CPU design by learning from input-output examplesProceedings of the Thirty-Third International Joint Conference on Artificial Intelligence10.24963/ijcai.2024/425(3843-3853)Online publication date: 3-Aug-2024
https://dl.acm.org/doi/10.24963/ijcai.2024/425
Xiao CDeng YYang ZChen RWang HZhao JDai HWang LTang YXu W(2024)LLM-based Processor Verification: A Case Study for Neuromorphic Processor2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546707(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546707
Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Jin SLi YChen LShi G(2024)SSFuzz:Generating syntactic and semantic seeds for RISC-V processorsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658712(421-426)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658712
Ma RYang YLiu ZZhang JLi MHuang JLuo G(2024)VerilogReader: LLM-Aided Hardware Test Generation2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691801(1-5)Online publication date: 28-Jun-2024
https://doi.org/10.1109/LAD62341.2024.10691801
Liu ALu TXi YLiu YLiu P(2024)Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States2024 IEEE International Test Conference (ITC)10.1109/ITC51657.2024.00015(36-40)Online publication date: 3-Nov-2024
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Das SPatel HKarfa CBellamkonda KReddy RPuri DJain ASur APrajapati P(2024)RTL Simulation Acceleration with Machine Learning Models2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528688(1-7)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528688
Wang WLiu P(2024)A Consistency Testing Method for Revealing RISC-V Processor's Undocumented Instructions2024 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST63913.2024.10838390(1-6)Online publication date: 16-Dec-2024
https://doi.org/10.1109/AsianHOST63913.2024.10838390
Yadav DBhagat PBeniwal PSaurabh S(2024)Codriver: A Tool for Coverage-Driven Functional Verification of RISC-V ProcessorsVLSI for Embedded Intelligence10.1007/978-981-97-3756-7_13(157-169)Online publication date: 28-Oct-2024
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Shen SLiu YZhang LSong FWu Z(2024)Formal Verification of RISC-V Processor Chisel DesignsDependable Software Engineering. Theories, Tools, and Applications10.1007/978-981-96-0602-3_8(142-160)Online publication date: 25-Nov-2024
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