Abstract
We present a fast shared memory multiprocessor with uniform memory access time. A first prototype (SB-PRAM) is running with 4 processors, a 128 processor version is under construction. A second implementation (HPP) using latest VLSI technology and high speed links shall run at a speed of 96 MHz. To achieve this speed, we first investigate a re-design of the hardware of the SB-PRAM. We then balance processor speed and memory bandwidth by investigating the relation between local computation and global memory access in several benchmark applications. On numerical codes such as Linpack 2 resp. 8 GFlop/s shall be possible with 128 resp. 512 processors, thus approaching processor performance of an Intel Paragon XPS. On non-numerical codes, i.e., circuit simulation and ray tracing, we achieve speedups over a one processor SGI challenge of 35 and 81 for 128 processors and 140 and 327 for 512 processors.
Research partly funded by the German Science Foundation (DFG) through SFB 124, TP D4.
Supported by a DFG Habilitation Fellowship.
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© 1996 Springer-Verlag Berlin Heidelberg
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Formella, A., Keller, J., Walle, T. (1996). HPP: A high performance PRAM. In: Bougé, L., Fraigniaud, P., Mignotte, A., Robert, Y. (eds) Euro-Par'96 Parallel Processing. Euro-Par 1996. Lecture Notes in Computer Science, vol 1124. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0024732
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DOI: https://doi.org/10.1007/BFb0024732
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