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Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip Yue QIAN Zhonghai LU Wenhua DOU Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E92-A No.12 pp.3211-3220 Publication Date: 2009/12/01 Online ISSN: 1745-1337 DOI: 10.1587/transfun.E92.A.3211 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: delay bounds, performance analysis, network calculus, network-on-chip, Full Text: PDF(1MB)>>
Summary: We investigate per-flow flit and packet worst-case delay bounds in on-chip wormhole networks. Such investigation is essential in order to provide guarantees under worst-case conditions in cost-constrained systems, as required by many hard real-time embedded applications. We first propose analysis models for flow control, link and buffer sharing. Based on these analysis models, we obtain an open-ended service analysis model capturing the combined effect of flow control, link and buffer sharing. With the service analysis model, we compute equivalent service curves for individual flows, and then derive their flit and packet delay bounds. Our experimental results verify that our analytical bounds are correct and tight. | ||||||||||
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