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Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk

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MEMOCODE '03: Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design

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Published: 24 June 2003 Publication History

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Bluespec has an execution model based on atomic actions.This model is quite different from traditional hardwaredescription languages like Verilog, VHDL and SystemC.Its also different from software languages like C andJava. Bluespec is based on research at MIT in using TermRewriting Systems (TRS) for hardware descriptions and wasdeveloped into an "industrial strength" language and compilerby the Sandburst Corporation. Bluespec, because ofits execution model, strong typing, and object orientation,can raise the level of hardware design significantly withoutcompromising the ability to synthesize efficient hardware.In this talk I will outline how and why Bluespec improvesthe chip design process by giving examples from microprocessorand other complex chips.

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Koeplinger DFeldman MPrabhakar RZhang YHadjis SFiszel RZhao TNardi LPedram AKozyrakis COlukotun K(2018)Spatial: a language and compiler for application acceleratorsACM SIGPLAN Notices10.1145/3296979.319237953:4(296-311)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192379
Koeplinger DFeldman MPrabhakar RZhang YHadjis SFiszel RZhao TNardi LPedram AKozyrakis COlukotun KFoster JGrossman D(2018)Spatial: a language and compiler for application acceleratorsProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192379(296-311)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192379
(2013)Translating synchronous guarded actions to interleaved guarded actionsProceedings of the Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign10.5555/3041405.3041499(167-176)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.5555/3041405.3041499
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Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk

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MEMOCODE '03: Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design

June 2003

ISBN:0769519237

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IEEE Computer Society

United States

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Published: 24 June 2003

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Koeplinger DFeldman MPrabhakar RZhang YHadjis SFiszel RZhao TNardi LPedram AKozyrakis COlukotun K(2018)Spatial: a language and compiler for application acceleratorsACM SIGPLAN Notices10.1145/3296979.319237953:4(296-311)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192379
Koeplinger DFeldman MPrabhakar RZhang YHadjis SFiszel RZhao TNardi LPedram AKozyrakis COlukotun KFoster JGrossman D(2018)Spatial: a language and compiler for application acceleratorsProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192379(296-311)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192379
(2013)Translating synchronous guarded actions to interleaved guarded actionsProceedings of the Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign10.5555/3041405.3041499(167-176)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.5555/3041405.3041499
Adler MFleming KParashar APellauer MEmer JWawrzynek JCompton K(2011)Leap scratchpadsProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950421(25-28)Online publication date: 27-Feb-2011
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Ko SGupta IJo Y(2008)A new class of nature-inspired algorithms for self-adaptive peer-to-peer computingACM Transactions on Autonomous and Adaptive Systems10.1145/1380422.13804263:3(1-34)Online publication date: 13-Aug-2008
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Ladan-Mozes ELeiserson CMeyer auf der Heide FShavit N(2008)A consistency architecture for hierarchical shared cachesProceedings of the twentieth annual symposium on Parallelism in algorithms and architectures10.1145/1378533.1378536(11-22)Online publication date: 1-Jun-2008
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Oliveira MWoodcock J(2007)Automatic generation of verified concurrent hardwareProceedings of the formal engineering methods 9th international conference on Formal methods and software engineering10.5555/1775348.1775371(286-306)Online publication date: 14-Nov-2007
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Thompson SMycroft AHatcliff JTip F(2006)Bit-level partial evaluation of synchronous circuitsProceedings of the 2006 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation10.1145/1111542.1111548(29-37)Online publication date: 9-Jan-2006
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Bhattacharya RGerman SGopalakrishnan G(2006)Exploiting symmetry and transactions for partial order reduction of rule based specificationsProceedings of the 13th international conference on Model Checking Software10.1007/11691617_15(252-270)Online publication date: 30-Mar-2006
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VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture

Bluespec System Verilog: efficient, correct RTL from high level specifications

Bluespec and Haskell

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