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Area-time efficient addition in charge based technology

Published: 29 June 1981 Publication History

Abstract

Using the model developed by Mead and Conway for charge based technology, a methodology for the production of area-time efficient adders which imbeds the buffering required to drive large loads caused by the carry-lookahead tree has been developed. This methodology can be used to produce an O(logN) time and O(NlogN) area layout. Additionally, an algorithm was written to produce minimal silicon area layouts for a given time bound. This algorithm involves optimization at both the cellular level and the layout level in an iterative fashion to allow the relevant technological parameters to play a role in the cellular design phase. Results of the algorithm including examples and an area-time curve for a 48 bit adder using typical 5 micron NMOS [MeCo80] are displayed.

References

[1]
Bilgory, A. and Gajski D.D., "Automatic Cell Generation for Recurrence Structures," University of Illinois at Urbana-Champaign, Department of Computer Science, Report UIUCCDS-R-R80-1040, November, 1980.
[2]
Bilgory, A. and Gajski D.D., "An Algorithm for Efficient Layouts of Parallel Suffix Solutions," Submitted to the International Conference on Parallel Processing, 1981.
[3]
Brent, R. P., "On The Addition of Binary Numbers," IEEE Transactions on Computers, C-19 (1970), pp. 758,759.
[4]
Brent, R. P. and H. T. Kung, "A Regular Layout For Binary Adders," Technical Report, Dept. of Computer Science, Carnegie-Mellon University, July, 1979.
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Chen, S. C. and D. J. Kuck, "Combinational Circuit Synthesis With Time and Component Bounds," IEEE Transactions on Computers, Vol C-26, (1977), pp. 712-726.
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Ladner, R. E. and M. J. Fischer, "Parallel Prefix Computation," Proc. 1977 International Conference on Parallel Processing, 1977, pp. 213-223.
[7]
Mead, C. A. and L. A. Conway, Introduction to VLSI Systems, Addison Wesley, 1980.
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Mead, C. A. and M. Rem, "Cost and Performance of VLSI Computing Structures," IEEE Transactions on Electron Devices, ED-26, April 1979, pp. 533-540.
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Mohsen, A. M. and C. A. Mead, "Delay-Time Optimization for Driving and Sensing of Signals on High-Capacitance Paths of VLSI Systems," IEEE Transactions on Electron Devices, ED-26, April 1979, pp. 542-548.
[10]
Ruelli, A. E., S. Woff, and G. Goertzel, "Analytical Power/Timing Optimization Technique for Digital Systems," Journal of Design Automation and Fault Tolerant Computing, Vol. 1, pp. 145-164 (1978).
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Winograd, S., "On Time Required to Perform Addition," JACM, 12 (1965), pp. 277-285.
[12]
Vergines, Bernard, "Macro Design Algorithms for LSI Custom Circuitry," IBM Journal of Research and Development, Vol. 24, No. 5, September, 1980.

Cited By

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  • (2003)Constructive threshold logic additionProceedings of the 2003 joint international conference on Artificial neural networks and neural information processing10.5555/1767129.1767229(745-752)Online publication date: 26-Jun-2003

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cover image ACM Conferences
DAC '81: Proceedings of the 18th Design Automation Conference
June 1981
899 pages

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IEEE Press

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Published: 29 June 1981

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  • (2003)Constructive threshold logic additionProceedings of the 2003 joint international conference on Artificial neural networks and neural information processing10.5555/1767129.1767229(745-752)Online publication date: 26-Jun-2003

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