Article

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees

Authors:

C. Zhuang,

Y. Kajitani,

K. Sakanushi,

L. JinAuthors Info & Claims

DATE '02: Proceedings of the conference on Design, automation and test in Europe

Page 61

Published: 04 March 2002 Publication History

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Abstract

After the discussion on the difference between floorplanningand packing in VLSI placement design, this paperadapts the floorplanner that is based on the Q-sequence to apacking algorithm. For the purpose, some empty room insertionis required to guarantee not to miss the optimum packing.To increase the performance in packing, a new move that perturbsthe floorplan is introduced in terms of the Parenthesis-TreePair. A Simulated Anealing based packing search algorithmwas implemented. Experimental results showed theeffect of empty room insertion.

Cited By

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Funke JHougardy SSchneider J(2016)An exact algorithm for wirelength optimal placements in VLSI designIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.00152:C(355-366)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.001
Nakatake SKoh CSze C(2013)Practicality on placement given by optimality of packingProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451931(59-60)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451931
Cheng LDeng LWong MTang T(2005)Floorplanning for 3-D VLSI designProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120899(405-411)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120899
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Information

Published In

DATE '02: Proceedings of the conference on Design, automation and test in Europe

March 2002

1072 pages

ISBN:0769514715

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 March 2002

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DATE02

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SIGDA

DATE02: Design, Automation and Test in Europe

March 4 - 8, 2002

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all

Funke JHougardy SSchneider J(2016)An exact algorithm for wirelength optimal placements in VLSI designIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.00152:C(355-366)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.001
Nakatake SKoh CSze C(2013)Practicality on placement given by optimality of packingProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451931(59-60)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451931
Cheng LDeng LWong MTang T(2005)Floorplanning for 3-D VLSI designProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120899(405-411)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120899
Wang RDong SHong XTang T(2005)An improved P-admissible floorplan representation based on Corner Block ListProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120837(1115-1118)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120837
Chan HAdya SMarkov IGroeneveld PScheffer L(2005)Are floorplan representations important in digital design?Proceedings of the 2005 international symposium on Physical design10.1145/1055137.1055164(129-136)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055164
Liu JZhong WJiao L(2005)Moving block sequence and organizational evolutionary algorithm for general floorplanningProceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part I10.1007/11596448_34(238-246)Online publication date: 15-Dec-2005
https://dl.acm.org/doi/10.1007/11596448_34
Wu YChan C(2005)On improved least flexibility first heuristics superior for packing and stock cutting problemsProceedings of the Third international conference on StochasticAlgorithms: foundations and applications10.1007/11571155_8(70-81)Online publication date: 20-Oct-2005
https://dl.acm.org/doi/10.1007/11571155_8
Zhang XKajitani YImai M(2004)Space-planning: placement of modules with controlled empty area by single-sequenceProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015099(25-30)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015099
Zhuang CSakanushi KJin LKajitani YYasuura H(2003)An extended representation of Q-sequence for optimizing channel-adjacency and routing-costProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119837(338-341)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119837
Kodama CFujiyoshi KYasuura H(2003)Selected sequence-pairProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119836(331-337)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119836

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