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Is wire tapering worthwhile?

Authors:

Charles J. Alpert,

Anirudh Devgan,

Stephen T. QuayAuthors Info & Claims

ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Pages 430 - 436

Published: 07 November 1999 Publication History

Abstract

Wire sizing and buffer insertion/sizing are critical optimizations in deep submicron design. The past years have seen several studies of buffer insertion, wire sizing, and their simultaneous optimization. When wiring long interconnect, tapering, i.e., reducing the wire width as the distance from the driver increases, has proven effective. However, tapering is not widely utilized in industry since it is difficult to integrate into a complete routing methodology. This work examines the benefits of wire sizing with tapering when combined with buffer insertion. We perform several experiments with actual IBM technologies. Results indicate that wire tapering reduces delay typically by less than 5% compared to uniform wire sizing, when buffers can be inserted. Consequently, we suggest that it may not be worthwhile to maintain a routing methodology that supports wire tapering.

References

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C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer Insertion for Noise and Delay Optimization", 35th IEEE/ACM Design Automation Conference, 1998, pp. 362-367.

Digital Library

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C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer Insertion with Accurate Gate and Interconnect Delay Computation", 36th IEEE/ACM Design Automation Conference, 1999, pp. 479- 484.

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C.-E Chen, Y.-E Chen, D. F. Wong, "Optimal Wire-sizing Formula under the Elmore Delay Model", 33rd IEEE/ACM Design Automation Conference., 1996, pp. 487-490.

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C.-E Chen, Y.-E Chen, D. F. Wong, "Optimal Wire-sizing Function with Fringing Capacitance Consideration", 34th IEEE/ACM Design Automation Conf., 1997, pp. 604-607.

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Cited By

Hanchate NRanganathan NMalik SFix LKahng A(2004)A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizingProceedings of the 41st annual Design Automation Conference10.1145/996566.1142988(711-739)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.1142988
Albrecht CKahng AMandoiu IZelikovsky A(2002)Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire SizingProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835503Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835503
Kahng AStroobandt DStroobandt DChristie PKahng A(2000)Wiring layer assignments with consistent stage delaysProceedings of the 2000 international workshop on System-level interconnect prediction10.1145/333032.333041(115-122)Online publication date: 8-Apr-2000
https://dl.acm.org/doi/10.1145/333032.333041

Index Terms

Is wire tapering worthwhile?

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Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

November 1999

613 pages

ISBN:0780358325

Sponsors

IEEE-EDS: Electronic Devices Society
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

Publisher

IEEE Press

Publication History

Published: 07 November 1999

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ICCAD '99

Sponsor:

IEEE-EDS
SIGDA
IEEE-CAS
IEEE-CS

ICCAD '99: The International Conference on Computer Aided Design.

November 7 - 11, 1999

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Hanchate NRanganathan NMalik SFix LKahng A(2004)A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizingProceedings of the 41st annual Design Automation Conference10.1145/996566.1142988(711-739)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.1142988
Albrecht CKahng AMandoiu IZelikovsky A(2002)Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire SizingProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835503Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835503
Kahng AStroobandt DStroobandt DChristie PKahng A(2000)Wiring layer assignments with consistent stage delaysProceedings of the 2000 international workshop on System-level interconnect prediction10.1145/333032.333041(115-122)Online publication date: 8-Apr-2000
https://dl.acm.org/doi/10.1145/333032.333041

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