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Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise

Authors:

Janardhan Rao Doppa,

Partha Pratim Pande,

Krishnendu ChakrabartyAuthors Info & Claims

DATE '17: Proceedings of the Conference on Design, Automation & Test in Europe

Pages 1366 - 1371

Published: 27 March 2017 Publication History

Abstract

A 3D network-on-chip (3D NoC) is an enabler for the design of high-performance and energy-efficient manycore chips. Most popular 3D NoCs utilize the Through-Silicon-Via (TSV)-based vertical links (VLs) as the communication pillars between the planar dies. However, the TSVs in a 3D NoC may fail due to both workload-induced stress and crosstalk capacitance. This failure negatively affects the overall achievable performance of the 3D NoC. In this work, we analyze the joint effects of workload-induced stress and crosstalk on the TSV mean-time-to-failure (MTTF) and hence the 3D NoC lifetime. We demonstrate that if we only consider the effects of electromigration on the TSVs due to workload-induced stress then the estimated MTTF and the subsequently lifetime of 3D NoC are too optimistic. Due to the combined effects of workload and crosstalk noise, the lifetime of 3D NoC reduces significantly. Subsequently, we demonstrate that a spare TSV allocation methodology considering the joint effects of workload and crosstalk noise enhances the lifetime of the 3D NoC by a factor of 4.6 compared to when only the workload is considered for a given spare budget of 5%.

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Cited By

Das SBasu KDoppa JPande PKarri RChakrabarty KLu ZVangal SXu JBogdan P(2018)Abetting planned obsolescence by aging 3D networks-on-chipProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306629(1-8)Online publication date: 4-Oct-2018
https://dl.acm.org/doi/10.5555/3306619.3306629

Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise
1. Computer systems organization
2. General and reference
  1. Cross-computing tools and techniques

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Published In

cover image Guide Proceedings

DATE '17: Proceedings of the Conference on Design, Automation & Test in Europe

March 2017

1814 pages

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 27 March 2017

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Cited By

Das SBasu KDoppa JPande PKarri RChakrabarty KLu ZVangal SXu JBogdan P(2018)Abetting planned obsolescence by aging 3D networks-on-chipProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306629(1-8)Online publication date: 4-Oct-2018
https://dl.acm.org/doi/10.5555/3306619.3306629

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