A new approach for partitioning VLSI circuits on transistor level
Pages 64 - 67
Abstract
For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects between the subcircuits and balanced subcircuit sizes is presented. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.
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- A new approach for partitioning VLSI circuits on transistor level
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Published In
July 1997184 pages
Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
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- SCS: Society for Computer Simulation
- SIGSIM: ACM Special Interest Group on Simulation and Modeling
- IEEE: Institute of Electrical and Electronics Engineers
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IEEE Computer Society
United States
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Published: 01 June 1997
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PADS '97 Paper Acceptance Rate 27 of 47 submissions, 57%;
Overall Acceptance Rate 398 of 779 submissions, 51%
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