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EDA solutions to new-defect detection in advanced process technologies

Published: 12 March 2012 Publication History

Abstract

For decades, EDA test generation tools for digital logic have relied on the Stuck-At fault model, despite the fact that process technologies moved forward from TTL (for which the Stuck-At fault model was originally developed) to nanometer-scale CMOS. Under pressure from their customers, especially in quality-sensitive application domains such as automotive, in recent years EDA tools have made great progress in improving their detection capabilities for new defects in advanced process technologies. For this Hot-Topic Session, we invited the three major EDA vendors to present their recent greatest innovations in hiqh-quality automatic test pattern generation, as well as their lead customers to testify of actual production results.

References

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B. Kruseman et al. On Hazard-Free Patterns for Fine-Delay Fault Testing. In Proceedings IEEE International Test Conference (ITC), pages 213--222, October 2004.
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H. Villacorta et al. Reliability Analysis of Small Delay Defects in Vias Located in Signal Paths. pages 1--6, November 2010.
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R. Turakhia et al. Silicon Evaluation of Longest Path Avoidance Testing for Small Delay Defects. In Proceedings IEEE International Test Conference (ITC), pages 1--10, October 2007.
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cover image ACM Conferences
DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe
March 2012
1690 pages
ISBN:9783981080186

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 12 March 2012

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DATE '12
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE '12: Design, Automation and Test in Europe
March 12 - 16, 2012
Dresden, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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March 31 - April 2, 2025
Lyon , France

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