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research-article

Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Authors:

Satoshi GotoAuthors Info & Claims

ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Pages 772 - 775

Published: 21 January 2008 Publication History

Abstract

The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

References

[1]

F.Balasa and K. Lampaert "Symmetry within the Sequence-Pair Representation in the Context of Placement for Analog Design," IEEETCAD, vol. 19. pp. 721--731. 2000

Digital Library

[2]

F.Balasa, et al. "Efficient solution space exploration based on segment trees in analog placement for analog placement with symmetry constraints," ICCAD. pp. 497--502. 2002

Digital Library

[3]

Jai-Ming Lin; Guang-Ming Wu; Yao-Wen Chang; Jen-Hui Chuang; "Placement with symmetry constraints for analog layout design using TCG-S" Proceedings of the ASP-DAC 2005. Asia and South Pacific, Volume 2, pp. 1135--1138.

Digital Library

[4]

E.Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli, "Automation of IC layout with analog constraints," IEEE Trans. Computer-Aided Design, vol. 15, pp. 923--942. 1996

Digital Library

[5]

M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433--1439, May 1989.

[6]

K. Bult, "Analog design in deep sub-micron CMOS," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2000, pp. 11--17.

[7]

W. Sansen, M. Steyaert, V. Peluso, and E. Peeters, "Toward sub 1 V analog integrated circuits in submicron standard CMOS technologies," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb.1998, pp. 186--187.

[8]

P. Kinget and M. Steyaert, "Impact of transistor mismatch on the speed-accuracy-power tradeoff of analog CMOS circuits," in Proc .IEEE Custom Integrated Circuits Conf. (CICC), May 1996, pp.333--336.

[9]

Asheghi, M, Sverdrup, P.; Goodson, K. E.," Thermal modeling of thin-film SOI transistors" SOI Conference, 1999. Proceedings. 1999 IEEE International 4--7 Oct. 1999 Page(s):28--29

[10]

B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan, and M. J. Uren, "Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques" IEEE Trans. Electron Devices, vol. 43, pp. 2240--2248, Dec.1996

[11]

Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong, "Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation" ACM/IEEE ASP-DAC 2007 pp191--196

Digital Library

[12]

T.-H. Yeh, J. Lin, S.-C. Wong, H. Huang, and J. Sun, "Mis-match characterization of 1.8 V and 3.3 V devices in 0.18 _m mixed signal CMOS technology," in Proc. IEEE Int. Conf. Microelectronic Test Structures, Mar. 2001, pp. 77--82

[13]

J. Bastos, M. Steyaert, R. Roovers, P. Kinget, W. Sansen, B. Graindourze, N. Pergoot, and E. Janssens, "Mismatch characterization of small size MOS transistors" in Proc. IEEE Int. Conf. Microelectronic Test Structures, Mar. 1995, pp. 271--276.

[14]

J. Bastos, M. Steyaert, A. Pergoot, andW. Sansen, "Mismatch characterization of submicron MOS transistors," Analog Integrat. Circuits Signal Process., vol. 12, no. 2, pp. 95--106, Feb. 1997.

Digital Library

[15]

J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. Norwell, MA: Kluwer Academic, 1991.

[16]

S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.

[17]

Tenbroek, B. M.; Lee, M. S. L.; Redman-White, W.; Bunyan, R. J. T.; Uren, M. J.; "Impact of self-heating and thermal coupling on analog circuits in SOI CMOS" Solid-State Circuits, IEEE Journal of Volume 33, Issue 7, July 1998 pp.1037--1046

[18]

Kinget, P. Steyaert, M. "Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits", :Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, On page(s): 333--336

[19]

Qingsheng Hao; Sheqin Dong;Song Chen; Xianlong Hong; Yi Su; Zhiyi Qu; "Constraints generation for analog circuits layout" 2004 International Conference on Communication, Circuit and System, pp. 1339--1343

Cited By

Huang CWey CChen JLuo P(2015)Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCsACM Transactions on Design Automation of Electronic Systems10.1145/277087221:1(1-17)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2770872
Huang CWey CChen JLuo P(2013)Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuitsACM Transactions on Design Automation of Electronic Systems10.1145/253439419:1(1-13)Online publication date: 20-Dec-2013
https://dl.acm.org/doi/10.1145/2534394
Lin PZhang HWong MChang Y(2009)Thermal-driven analog placement considering device matchingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630064(593-598)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630064

Index Terms

Symmetry constraint based on mismatch analysis for analog layout in SOI technology
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference

January 2008

812 pages

ISBN:9781424419227

General Chair:
Chong-Min Kyung,
Program Chairs:
Kiyoung Choi,
Soonhoi Ha

Sponsors

IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEEK: The Institute of Electronics Engineers of Korea

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 21 January 2008

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Research-article

Conference

ASPDAC '08

Sponsor:

SIGDA
IEEK

ASPDAC '08: Asia and South Pacific Design Automation Conference

January 21 - 24, 2008

Seoul, Korea

Acceptance Rates

ASP-DAC '08 Paper Acceptance Rate 122 of 350 submissions, 35%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Huang CWey CChen JLuo P(2015)Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCsACM Transactions on Design Automation of Electronic Systems10.1145/277087221:1(1-17)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2770872
Huang CWey CChen JLuo P(2013)Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuitsACM Transactions on Design Automation of Electronic Systems10.1145/253439419:1(1-13)Online publication date: 20-Dec-2013
https://dl.acm.org/doi/10.1145/2534394
Lin PZhang HWong MChang Y(2009)Thermal-driven analog placement considering device matchingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630064(593-598)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630064

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