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ReSP: a non-intrusive transaction-level reflective MPSoC simulation platform for design space exploration

Published: 21 January 2008 Publication History

Abstract

This paper presents ReSP (Reflective Simulation Platform), a Transaction-Level multi-processor simulation platform based on SystemC and Python; SystemC is a standard language for system modeling and verification, and Python provides the platform with reflective capabilities. These are employed to give the designer an easy way to specify the architecture of a system, simulate the given configuration and perform automatic analysis on it. ReSP enables SystemC and Python interoperability through automatic Python wrapper generation. We show that the overhead associated with the Python intermediate layer is around 1%, therefore execution speed is not compromised. The advantages of our approach are: (a) easy integration of external IPs (b) fine grain control of the simulation (c) effortless integration of tools for system analysis and design space exploration. A case study shows how the platform can be extended to support system reliability assessment.

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Cited By

View all
  • (2014)A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded SystemsProceedings of the 33rd International Conference on Computer Safety, Reliability, and Security - Volume 866610.1007/978-3-319-10506-2_1(1-16)Online publication date: 10-Sep-2014
  • (2012)SESAM/Par4AllProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162133(9-16)Online publication date: 23-Jan-2012
  • (2010)SCEMITProceedings of the 47th Design Automation Conference10.1145/1837274.1837333(228-233)Online publication date: 13-Jun-2010
  • Show More Cited By

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        cover image ACM Conferences
        ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference
        January 2008
        812 pages
        ISBN:9781424419227

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        IEEE Computer Society Press

        Washington, DC, United States

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        Published: 21 January 2008

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        ASP-DAC '08 Paper Acceptance Rate 122 of 350 submissions, 35%;
        Overall Acceptance Rate 466 of 1,454 submissions, 32%

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        View all
        • (2014)A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded SystemsProceedings of the 33rd International Conference on Computer Safety, Reliability, and Security - Volume 866610.1007/978-3-319-10506-2_1(1-16)Online publication date: 10-Sep-2014
        • (2012)SESAM/Par4AllProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162133(9-16)Online publication date: 23-Jan-2012
        • (2010)SCEMITProceedings of the 47th Design Automation Conference10.1145/1837274.1837333(228-233)Online publication date: 13-Jun-2010
        • (2009)Dynamic Electronic Design Automation concept, benefit and frameworkProceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human10.1145/1655925.1656122(1086-1090)Online publication date: 24-Nov-2009
        • (2009)ReSPIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203026828:12(1857-1869)Online publication date: 1-Dec-2009
        • (2008)Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-designProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450138(7-12)Online publication date: 19-Oct-2008

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