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Article

Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508

Authors:

Riccardo Mariani,

Gabriele Boschi,

Federico ColucciAuthors Info & Claims

DATE '07: Proceedings of the conference on Design, automation and test in Europe

Pages 492 - 497

Published: 16 April 2007 Publication History

Abstract

This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the IEC 61508, an international norm for the functional safety of electronic safety-related systems, of which an overview is given in the paper. The methodology is based on a theory to decompose a digital circuit in "sensible zones" and a tool that automatically extracts these sensible zones from the RTL description. It includes as well a spreadsheet to compute the metrics required by the IEC norm such Diagnostic Coverage and Safe Failure Fraction. The FMEA results are validated by using another tool suite including a fault injection environment. The paper explains how to take benefits of the information provided by such approach and as example it is described how the methodology has been applied to design memory sub-systems to be used in fault robust microcontrollers for automotive applications. This methodology has been approved by TÜV-SÜD as the flow to assess and validate the Safe Failure Fraction of a given SoC in adherence to IEC 61508

References

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J.C Laprie, "Dependable Computing and Fault Tolerance Concepts and Terminology", IEEE Computer, 1985

[2]

H. Tahne, "Safe and Reliable Computer Control: Systems Concepts and Methods", Mech. Lab, Univ. Stock, 1996

[3]

CEI International Standard IEC 61508, 1998--2000

[4]

S. Brown, "Overview of IEC 61508 Design of electrical/electronic/programmable electronic safetyrelated systems", Computing & Control Engineering Journal February 2000, pages 6--12

[5]

R. E. McDermott et al, "The Basic of FMEA", Quality Resources Press, 1996

[6]

R. Mariani, G. Boschi, "A System Level Approach for Embedded Memory Robustness" Special Issue: Papers selected from the 1st International Conference on Memory Technology and Design - ICMTD'05.

[7]

R. Mariani, M. Chiavacci, S. Motto, "Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor", European Patent, EP1496435

[8]

R. Mariani, P. Fuhrmann, B. Vittorelli, "Cost-effective Approach to Error Detection for an Embedded Automotive Platform", SAE 2006 World Congress & Exhibition, April 2006, Detroit, MI, USA

[9]

www.fr.yogitech.com

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http://www.cadence.com/products/digital_ic/encountertest

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IEEE standard 1647, http://www.ieee1647.org/

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S. Mukherjee et al. "Cache scrubbing in Microprocessors: Mith or Necessaity?", 2004

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S. Mukherjee et al. "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor", 2003

Digital Library

[15]

M. Spica, "Do we need anything more than single bit error correction (ECC)?", 2004

[16]

R. Mariani, "A Platform-based Technology For Fault-robust Soc Design", IP/SOC 2006 Conference, December 2006, Grenoble, France

[17]

R. Mariani, P. Fuhrmann, B. Vittorelli, "Fault-Robust microcontrollers for automotive applications", 12th IEEE International On-Line Testing Symposium - 12 July 2006 - Como, Italy

Digital Library

Cited By

Rambo ETschiene ADiemer JAhrendts LErnst RFettweis GNebel W(2014)Failure analysis of a network-on-chip for real-time mixed-critical systemsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617010(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617010
Papadimitriou AHély DBeroulle VMaistri PLeveugle RFettweis GNebel W(2014)A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacksProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616859(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616859
Chen YHsu CLeu K(2009)Analysis of system bus transaction vulnerability in systemC TLM design platformProceedings of the 3rd WSEAS international conference on Computer engineering and applications10.5555/1519432.1519487(284-289)Online publication date: 10-Jan-2009
https://dl.acm.org/doi/10.5555/1519432.1519487

Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508
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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '07: Proceedings of the conference on Design, automation and test in Europe

April 2007

1741 pages

ISBN:9783981080124

General Chair:
Rudy Lauwereins
IMEC and KULeuven, Belgium
,
Program Chair:
Jan Madsen
DTU, Denmark

Sponsors

The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 16 April 2007

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DATE07

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE07: Design, Automation and Test in Europe

April 16 - 20, 2007

Nice, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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DATE '25

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Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

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Citations

Cited By

Rambo ETschiene ADiemer JAhrendts LErnst RFettweis GNebel W(2014)Failure analysis of a network-on-chip for real-time mixed-critical systemsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617010(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617010
Papadimitriou AHély DBeroulle VMaistri PLeveugle RFettweis GNebel W(2014)A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacksProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616859(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616859
Chen YHsu CLeu K(2009)Analysis of system bus transaction vulnerability in systemC TLM design platformProceedings of the 3rd WSEAS international conference on Computer engineering and applications10.5555/1519432.1519487(284-289)Online publication date: 10-Jan-2009
https://dl.acm.org/doi/10.5555/1519432.1519487

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