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Article

Design and Evaluation of Hybrid Fault-Detection Systems

Authors:

George A. Reis,

Jonathan Chang,

Neil Vachharajani,

David I. August,

Shubhendu S. MukherjeeAuthors Info & Claims

ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture

Pages 148 - 159

https://doi.org/10.1109/ISCA.2005.21

Published: 01 May 2005 Publication History

Abstract

As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have primarily considered hardware-only and software-only fault-detection mechanisms to identify and mitigate the deleterious effects of transient faults. These two fault-detection systems, however, are extremes in the design space, representing sharp trade-offs between hardware cost, reliability, and performance. In this paper, we identify hybrid hardware/software fault-detection mechanisms as promising alternatives to hardware-only and software-only systems. These hybrid systems offer designers more options to fit their reliability needs within their hardware and performance budgets. We propose and evaluate CRAFT, a suite of three such hybrid techniques, to illustrate the potential of the hybrid approach. For fair, quantitative comparisons among hardware, software, and hybrid systems, we introduce a new metric, Mean Work To Failure, which is able to compare systems for which machine instructions do not represent a constant unit of work. Additionally, we present a new simulation framework which rapidly assesses reliability and does not depend on manual identification of failure modes. Our evaluation illustrates that CRAFT, and hybrid techniques in general, offer attractive options in the fault-detection design space.

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Cited By

Venkatesha SParthasarathi R(2024)Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and ReliabilityACM Computing Surveys10.1145/366367256:11(1-76)Online publication date: 28-Jun-2024
https://dl.acm.org/doi/10.1145/3663672
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https://dl.acm.org/doi/10.1145/3638249
dos Santos FRech P(2024)Can GPU performance increase faster than the code error rate?The Journal of Supercomputing10.1007/s11227-024-06119-480:12(16918-16946)Online publication date: 1-Aug-2024
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Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture

June 2005

541 pages

ISBN:076952270X

ACM SIGARCH Computer Architecture News Volume 33, Issue 2
ISCA 2005
May 2005
531 pages
ISSN:0163-5964
DOI:10.1145/1080695
Issue’s Table of Contents

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 May 2005

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Article

Conference

ISCA05

Sponsor:

SIGARCH

ISCA05: The 32nd Annual International Symposium on Computer Architecture 2005

June 4 - 8, 2005

Acceptance Rates

ISCA '05 Paper Acceptance Rate 45 of 194 submissions, 23%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

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The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

Venkatesha SParthasarathi R(2024)Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and ReliabilityACM Computing Surveys10.1145/366367256:11(1-76)Online publication date: 28-Jun-2024
https://dl.acm.org/doi/10.1145/3663672
Santos FCarro LVella FRech P(2024)Assessing the Impact of Compiler Optimizations on GPUs ReliabilityACM Transactions on Architecture and Code Optimization10.1145/363824921:2(1-22)Online publication date: 12-Jan-2024
https://dl.acm.org/doi/10.1145/3638249
dos Santos FRech P(2024)Can GPU performance increase faster than the code error rate?The Journal of Supercomputing10.1007/s11227-024-06119-480:12(16918-16946)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1007/s11227-024-06119-4
Sartor ALorenzon AKundu SKoren IBeck AKaeli DPericàs M(2018)Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performanceProceedings of the 15th ACM International Conference on Computing Frontiers10.1145/3203217.3203238(54-61)Online publication date: 8-May-2018
https://dl.acm.org/doi/10.1145/3203217.3203238
Stanley-Marbell PRinard M(2017)Error-Efficient Computing SystemsFoundations and Trends in Electronic Design Automation10.1561/100000004911:4(362-461)Online publication date: 18-Dec-2017
https://dl.acm.org/doi/10.1561/1000000049
Wibowo BAgrawal AStanton TTuck J(2016)An Accurate Cross-Layer Approach for Online Architectural Vulnerability EstimationACM Transactions on Architecture and Code Optimization10.1145/297558813:3(1-27)Online publication date: 17-Sep-2016
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Liu QJung CLee DTiwari D(2016)Compiler-Directed Soft Error Detection and Recovery to Avoid DUE and SDC via Tail-DMRACM Transactions on Embedded Computing Systems10.1145/293066716:2(1-26)Online publication date: 19-Dec-2016
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Didehban MShrivastava A(2016)nZDCProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898054(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898054
Upasani GVera XGonzalez A(2016)A Case for Acoustic Wave Detectors for Soft-ErrorsIEEE Transactions on Computers10.1109/TC.2015.241965265:1(5-18)Online publication date: 1-Jan-2016
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Liu QJung CLee DTiwari D(2015)CloverACM SIGPLAN Notices10.1145/2808704.275495950:5(1-10)Online publication date: 4-Jun-2015
https://dl.acm.org/doi/10.1145/2808704.2754959
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