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Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip

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R. LauwereinsAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10986

Published: 03 March 2003 Publication History

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Abstract

The ability to (re)schedule a task either in hardware or software will be an important asset in a reconfigurable systems-on-chip. To support this feature we have developed an infrastructure that, combined with a suitable design environment permits the implementation and management of hardware/software relocatable tasks. This paper presents the general scope of our research, and details the communication scheme, the design environment and the hardware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320x240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.

References

[1]

{1} J-Y. Mignolet, S. Vernalde, D. Verkest, R. Lauwereins, "Enabling hardware-software multitasking on a reconfigurable computing platform for networked portable multimedia appliances", Proceedings of the International Conference on Engineering Reconfigurable Systems and Architecture 2002, pages 116-122, Las Vegas, June 2002.

Google Scholar

[2]

{2} T. Marescaux, A. Bartic, D. Verkest, S. Vernalde and R. Lauwereins, "Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs", FPL'2002, pages 795- 805, Montpellier France.

Digital Library

Google Scholar

[3]

{3} O. Diessel, G. Wigley, "Opportunities for Operating Systems Research in Reconfigurable Computing", Technical report ACRC-99-018, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, August, 1999

Google Scholar

[4]

{4} S. Guccione, D. Levi, P. Sundararajan, "JBits: A Java-based Interface for Reconfigurable Computing", 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD).

Google Scholar

[5]

{5} G. Wigley, D. Kearney, "The Management of Applications for Reconfigurable Computing using an Operating System", In Proc. Seventh Asia-Pacific Computer Systems Architecture Conference, January 2002, ACS Press.

Digital Library

Google Scholar

[6]

{6} J. Burns, A. Donlin, J. Hogg, S. Singh, M. de Wit, "A Dynamic Reconfiguration Run-Time System", Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), Napa Valley, CA, April 1997.

Digital Library

Google Scholar

[7]

{7} H. Walder, M. Platzner, "Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform", Proceedings of the International Conference on Engineering Reconfigurable Systems and Architecture 2002, pages 24-30, Las Vegas, June 2002

Google Scholar

[8]

{8} www.imec.be/ocapi

Google Scholar

[9]

{9} G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Hardware/Software Partitioning of embedded system in OCAPI-xl", CODES'01, Copenhagen, Denmark, April 2001.

Digital Library

Google Scholar

[10]

{10} H. Simmler, L. Levinson, R. Männer, "Multitasking on FPGA Coprocessors", Proc. 10th Int'l Conf. Field Programmable Logic and Applications, pages 121-130, Villach, Austria, August 2000.

Digital Library

Google Scholar

[11]

{11} D. Lilja, "Partitioning Tasks Between a Pair of Interconnected Heterogeneous Processors: A Case Study", Concurrency: Practice and Experience, Vol. 7, No. 3, May 1995, pp. 209-223

Crossref

Google Scholar

[12]

{12} L. Levinson, R. Männer, M. Sesler, H. Simmler, "Preemptive Multitasking on FPGAs", Proceedings of the 2000 IEEE Symposium on Field Programmable Custom Computing Machines.

Digital Library

Google Scholar

[13]

{13} F. Vermeulen, L. Nachtergaele, F Catthoor, D. Verkest, H. De Man, "Flexible Hardware Acceleration for Multimedia Oriented Microprocessors", (accepted) IEEE Transactions on Very Large Scale Integration Systems.

Google Scholar

Cited By

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Bourge AMuller ORousseau F(2016)Generating Efficient Context-Switch Capable Circuits through Autonomous Design FlowACM Transactions on Reconfigurable Technology and Systems10.1145/299619910:1(1-23)Online publication date: 9-Dec-2016
https://dl.acm.org/doi/10.1145/2996199
Iturbe XBenkrid KHong CEbrahim ATorrego RArslan T(2015)Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)ACM Transactions on Reconfigurable Technology and Systems10.1145/26296398:1(1-35)Online publication date: 6-Mar-2015
https://dl.acm.org/doi/10.1145/2629639
Quan WPimentel AChatha KErnst RRaghunathan AIyer R(2014)A system-level simulation framework for evaluating task migration in MPSoCsProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656111(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656111
Show More Cited By

Index Terms

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
2. Hardware
  1. Integrated circuits
    1. Digital switches
      1. Logic families
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all

Bourge AMuller ORousseau F(2016)Generating Efficient Context-Switch Capable Circuits through Autonomous Design FlowACM Transactions on Reconfigurable Technology and Systems10.1145/299619910:1(1-23)Online publication date: 9-Dec-2016
https://dl.acm.org/doi/10.1145/2996199
Iturbe XBenkrid KHong CEbrahim ATorrego RArslan T(2015)Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)ACM Transactions on Reconfigurable Technology and Systems10.1145/26296398:1(1-35)Online publication date: 6-Mar-2015
https://dl.acm.org/doi/10.1145/2629639
Quan WPimentel AChatha KErnst RRaghunathan AIyer R(2014)A system-level simulation framework for evaluating task migration in MPSoCsProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656111(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656111
Krishnamurthy VPonpandi STyagi AGupta RMooney V(2011)A novel thread scheduler design for polymorphic embedded systemsProceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems10.1145/2038698.2038712(75-84)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2038698.2038712
Diguet JEustache YGogniat G(2011)Closed-loop--based self-adaptive Hardware/Software-Embedded systemsACM Transactions on Embedded Computing Systems10.1145/1952522.195253110:3(1-28)Online publication date: 5-May-2011
https://dl.acm.org/doi/10.1145/1952522.1952531
Götz MRettberg APereira CRammig F(2009)Run-time reconfigurable RTOS for reconfigurable systems-on-chipJournal of Embedded Computing10.5555/1516712.15167173:1(39-51)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.5555/1516712.1516717
Rincón FBarba JMoya FLópez JDondo J(2009)Transparent Dynamic Reconfiguration as a Service of a System-Level MiddlewareProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_29(281-286)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_29
Huang CHsiung P(2008)Software-controlled dynamically swappable hardware design in partially reconfigurable systemsEURASIP Journal on Embedded Systems10.1155/2008/2319402008(1-11)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1155/2008/231940
Eustache YDiguet JGebotys CMartin G(2008)Specification and OS-based implementation of self-adaptive, hardware/software embedded systemsProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450151(67-72)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450151
Tan HDeMara R(2008)A multilayer framework supporting autonomous run-time partial reconfigurationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.91755116:5(504-516)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.917551
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