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Article

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

Authors:

Dimitrios Velenis,

Marios C. Papaefthymiou,

Eby G. FriedmanAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10068

Published: 03 March 2003 Publication History

Abstract

The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A polynomial time algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay to the most critical data paths. Strategies for enhancing the physical layout of the clock tree to decrease delay uncertainty are also presented. Application of the methodology on benchmark circuits demonstrates clock tree topologies with decreased delay uncertainties of up to 90%. Techniques to enhance a clock tree layout have been applied on a set of benchmark circuits, yielding a reduction in delay uncertainty of up to 48%.

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Cited By

Chan THan KKahng ALee JNath SCavallaro JZhang TJones ALi H(2014)OCV-aware top-level clock tree optimizationProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591541(33-38)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591541
Abdelhadi AGinosar RKolodny AFriedman EBahar RLombardi FAtienza DBrunvand E(2010)Timing-driven variation-aware nonuniform clock mesh synthesisProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785487(15-20)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785487
Tawfik SKursun V(2010)Dual supply voltages and dual clock frequencies for lower clock power and suppressed temperature-gradient-induced clock skewIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201054918:3(347-355)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2010549
Show More Cited By

Index Terms

Reduced Delay Uncertainty in High Performance Clock Distribution Networks
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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DATE03

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SIGDA

DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Chan THan KKahng ALee JNath SCavallaro JZhang TJones ALi H(2014)OCV-aware top-level clock tree optimizationProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591541(33-38)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591541
Abdelhadi AGinosar RKolodny AFriedman EBahar RLombardi FAtienza DBrunvand E(2010)Timing-driven variation-aware nonuniform clock mesh synthesisProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785487(15-20)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785487
Tawfik SKursun V(2010)Dual supply voltages and dual clock frequencies for lower clock power and suppressed temperature-gradient-induced clock skewIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201054918:3(347-355)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2010549
Tawfik SKursun VMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distributionProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283795(62-67)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283795
Roberts WVelenis DQu GIsmail YNarayanan VZhou H(2006)Effects of process and environmental variations on timing characteristics of clocked registersProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127948(165-168)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127948
Hassan HAnis MElmasry M(2005)Design and optimization of MOS current mode logic for parameter variationsIntegration, the VLSI Journal10.5555/1062115.171208938:3(417-437)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/1062115.1712089
Venkataraman GSze CHu JTang T(2005)Skew scheduling and clock routing for improved tolerance to process variationsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120972(594-599)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120972
Roberts WVelenis D(2005)Parameter variation effects on timing characteristics of high performance clocked registersProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_52(508-517)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_52

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