research-article

Row-based area-array I/O design planning in concurrent chip-package design flow

Authors:

Ren-Jie Lee,

Hung-Ming ChenAuthors Info & Claims

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

Pages 837 - 842

Published: 25 January 2011 Publication History

Get Access

Abstract

IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this paper, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile which combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.

References

[1]

J. Wang, K. K. Muchherla and J. G. Kumar, "A Clustering Based Area I/O Planning for Flip-Chip Technology," In Proc. International Symposium on Quality Electronic Design, pp. 196--201, 2004.

Digital Library

Google Scholar

[2]

C.-Y. Chang and H.-M. Chen, "Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization," In IEEE Trans. on Very Large Scale Integration Systems, vol. 16, no. 1, pp. 108--112, Jan. 2008.

Digital Library

Google Scholar

[3]

C. Tan, D. Bouldin and P. Dehkordi, "Design Implementation of Intrinsic Area Array ICs," In Proc. Seventeenth Conference on Advanced Research in VLSI, pp. 82--93, 1997.

Digital Library

Google Scholar

[4]

V. Maheshwari, J. Darnauer, J. Ramirez and W. W.-M. Dai, "Design of FPGAs with Area I/O for Field Programmable MCM," In Proc. ACM International Symposium on Field-programmable gate arrays, pp. 17--23, 1995.

Digital Library

Google Scholar

[5]

J.-W. Fang, I.-J. Lin, Y.-W. Chang and J.-H. Wang, "A Network-Flow Based RDL Routing Algorithms for Flip-Chip Design," In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1417--1429, Aug. 2007.

Digital Library

Google Scholar

[6]

J.-W. Fang, C.-H. Hsu and Y.-W. Chang, "An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs," In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 98--110, Jan. 2009.

Digital Library

Google Scholar

[7]

H.-M. Chen, I-M. Liu and D.-F. Wong, "I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design," In IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2552--2556, Nov. 2006.

Digital Library

Google Scholar

[8]

J. Xiong, Y.-C. Wong, E. Sarto and L. He, "Constraint Driven I/O Planning and Placement for Chip-package Co-design," In Proc. Asia and South Pacific Design Automation Conference, pp. 207--212, 2006.

Digital Library

Google Scholar

[9]

J.-W. Fang and Y.-W. Chang, "Area-I/O Flip-Chip Routing for Chip-Package Co-Design," In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 518--522, 2008.

Digital Library

Google Scholar

[10]

K. Sheth, E. Sarto and J. McGrath, "The Importance of Adopting a Package-Aware Chip Design Flow," In Proc. ACM/IEEE Design Automation Conference, pp. 853--856, 2006.

Digital Library

Google Scholar

[11]

R.-J. Lee and H.-M. Chen, "Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign," In IEEE Trans. on Very Large Scale Integration Systems, vol. 17, no. 8, pp. 1087--1098, Aug. 2009.

Digital Library

Google Scholar

[12]

A. Fontanelli, S. Arrigoni, D. Raccagni and M. Rosin, "System-on-Chip (SoC) Requires IC and Package Co-Design and Co-Verification," In Proc. IEEE Custom Integrated Circuits Conference, pp. 319--322, 2002.

Google Scholar

[13]

C. Tan, D. Bouldin and P. Dehkordi, "An Intrinsic Area-Array Pad Router for ICs," In Proc. 10th Annual IEEE International ASIC Conference, pp. 265--269, 1997.

Google Scholar

[14]

T. Meister, J. Lienig and G. Thomke, "Novel Pin Assignment Algorithms for Components with Very High Pin Counts," In Proc. Design, Automation and Test in Europe, pp. 837--842, 2008.

Digital Library

Google Scholar

Cited By

View all

Liu WChang MWang T(2014)Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICsProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593142(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593142
Ho YChang Y(2013)Multiple chip planning for chip-interposer codesignProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488767(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488767
Lee HChang YGroeneveld PSciuto DHassoun S(2012)A chip-package-board co-design methodologyProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228557(1082-1087)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228557

Index Terms

Row-based area-array I/O design planning in concurrent chip-package design flow
1. Hardware

Recommendations

A study of row-based area-array I/O design planning in concurrent chip-package design flow

IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system ...
Area-I/O flip-chip routing for chip-package co-design
ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O's in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing ...
Area-I/O flip-chip routing for chip-package co-design considering signal skews

The area-input/output (I/O) flip-chip package provides a high chip-density solution to the demand of more I/Os in very large scale integration designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

January 2011

841 pages

ISBN:9781424475162

Publisher

IEEE Press

Publication History

Published: 25 January 2011

Check for updates

Qualifiers

Research-article

Conference

ASPDAC '11

Sponsor:

SIGDA
IEICE ESS

ASPDAC '11: 16th Asia and South Pacific Design Automation Conference

January 25 - 28, 2011

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
91
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 11 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Liu WChang MWang T(2014)Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICsProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593142(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593142
Ho YChang Y(2013)Multiple chip planning for chip-interposer codesignProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488767(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488767
Lee HChang YGroeneveld PSciuto DHassoun S(2012)A chip-package-board co-design methodologyProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228557(1082-1087)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228557

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

A study of row-based area-array I/O design planning in concurrent chip-package design flow

Area-I/O flip-chip routing for chip-package co-design

Area-I/O flip-chip routing for chip-package co-design considering signal skews