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Multi-operand adder synthesis on FPGAs using generalized parallel counters

Published: 18 January 2010 Publication History

Abstract

Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3; 2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compression trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show its effectiveness against existing approaches at GPC level and on Altera's Stratix III.

References

[1]
C. Wallace, "A suggestion for a fast multiplier," IEE Transactions on Electronic Computers, vol. EC-13, pp. 14--17, 1964.
[2]
L. Dadda, "Some schemes for parallel multipliers," Alta Frequenza, vol. 34, pp. 349--356, 1965.
[3]
V. G. Oklobdzija and D. Villeger, "Improving multiplier design by using improved column compression tree and optimized final adder in cmos technology," IEEE Transactions on VLSI Systems, vol. 3, no. 2, 1995.
[4]
P. Stelling, C. Martel, V. G. Oklobdzija, and R. Ravi, "Optimal circuits for parallel multipliers," IEEE Transaction on Computers, vol. 47, no. 3, pp. 273--285, 1998.
[5]
W. J. Stenzel and W. J. Kubitz, "A compact high-speed parallel multiplication scheme," IEEE Transaction on Computers, vol. C-26, pp. 948--957, 1977.
[6]
A. K. Verma and P. Ienne, "Automatic synthesis of compressor trees: Reevaluating large counters," in Design, Automation, and Test in Europe, 2007.
[7]
H. Parandeh-Afshar, P. Brisk, and P. Ienne., "Efficient synthesis of compressor trees on FPGAs," in Asia and South Pacific Design Automation Conference, 2008.
[8]
H. Parandeh-Afshar, P. Brisk, and P. Ienne, "Improving synthesis of compressor trees on FPGAs via integer linear programming," in Design, Automation, and Test in Europe, 2008.
[9]
L. Dadda, "On parallel digital multipliers," Reprinted from Alta Frequenza, vol. 45, pp. 547--580, 1976.
[10]
Altera Corp., "The Stratix III Device Handbook.

Cited By

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  • (2011)Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAsProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016854(217-222)Online publication date: 1-Aug-2011
  • (2011)Compressor tree synthesis on commercial high-performance FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/2068716.20687254:4(1-19)Online publication date: 28-Dec-2011

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cover image ACM Conferences
ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference
January 2010
920 pages
ISBN:9781605588377

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IEEE Press

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Published: 18 January 2010

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View all
  • (2011)Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAsProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016854(217-222)Online publication date: 1-Aug-2011
  • (2011)Compressor tree synthesis on commercial high-performance FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/2068716.20687254:4(1-19)Online publication date: 28-Dec-2011

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