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Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks

Published: 18 January 2010 Publication History

Abstract

Multiple memory banks with bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into the original programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert BSLs at different positions so that the overheads can be minimized. Minimizing code size and minimizing runtime overhead are two objectives investigated in this paper. Experiments show that the algorithms proposed can reduce the overhead caused by BSLs efficiently.

References

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Bernhard Scholz, Bernd Burgstaller, Jingling Xue, "Minimizing Bank Selection Instructions for Partitioned Memory Architectures," CASES06: 201--211, 2006.
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Yuan Mengting, Wu Guoqing, Yu Chao, "Optimizing Bank Selection Instructions by Using Shared Memory," ICESS2008: 447--450, 2008.
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Cited By

View all
  • (2013)Minimizing code size via page selection optimization on partitioned memory architecturesProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555741(1-10)Online publication date: 29-Sep-2013
  • (2013)Optimal placement of bank selection instructions in polynomial timeProceedings of the 16th International Workshop on Software and Compilers for Embedded Systems10.1145/2463596.2463598(23-30)Online publication date: 19-Jun-2013
  • (2013)Joint variable partitioning and bank selection instruction optimization for partitioned memory architecturesACM Transactions on Embedded Computing Systems (TECS)10.1145/2442116.244212612:3(1-27)Online publication date: 8-Apr-2013

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cover image ACM Conferences
ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference
January 2010
920 pages
ISBN:9781605588377

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IEEE Press

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Published: 18 January 2010

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2013)Minimizing code size via page selection optimization on partitioned memory architecturesProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555741(1-10)Online publication date: 29-Sep-2013
  • (2013)Optimal placement of bank selection instructions in polynomial timeProceedings of the 16th International Workshop on Software and Compilers for Embedded Systems10.1145/2463596.2463598(23-30)Online publication date: 19-Jun-2013
  • (2013)Joint variable partitioning and bank selection instruction optimization for partitioned memory architecturesACM Transactions on Embedded Computing Systems (TECS)10.1145/2442116.244212612:3(1-27)Online publication date: 8-Apr-2013

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