research-article

A hybrid packet-circuit switched on-chip network based on SDM

Authors:

Mehdi Modarressi,

Hamid Sarbazi-Azad,

Mohammad ArjomandAuthors Info & Claims

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 566 - 569

Published: 20 April 2009 Publication History

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Abstract

In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit-switched sub-network. The former directs packets according to the traditional packet-switching mechanism, while the latter forwards packets over circuits which are directly established between two non-adjacent nodes by bypassing the intermediate routers. A packet may switch between the subnetworks several times to reach its destination. The circuits are set up using a low-latency and low-cost setup-network. The network resources are split between the two sub-networks using Spatial-Division Multiplexing (SDM). The work aims to improve the power and performance metrics of Network-on-Chip (NoC) architectures and benefits from the power and scalability advantage of packet-switched NoCs and superior communication performance of circuit-switching. The evaluation results show a significant reduction in power and latency over a traditional packet-switched NoC.

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Cited By

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Sneps-Sneppe MNamiot D(2018)Time to Rethink the Power of Packet SwitchingProceedings of the 23rd Conference of Open Innovations Association FRUCT10.5555/3299905.3299955(369-374)Online publication date: 19-Nov-2018
https://dl.acm.org/doi/10.5555/3299905.3299955
Luo HWei SChen DGuo D(2014)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2014.05.00374:9(2818-2830)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1016/j.jpdc.2014.05.003
Xiao CFrank Chang MCong JGill MHuang ZLiu CReinman GWu H(2013)Stream arbitrationACM Transactions on Architecture and Code Optimization10.1145/2400682.24007199:4(1-27)Online publication date: 20-Jan-2013
https://dl.acm.org/doi/10.1145/2400682.2400719
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Information & Contributors

Information

Published In

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

April 2009

1776 pages

ISBN:9783981080155

General Chairs:
Luca Benini
University of Bologna, IT
,
Giovanni De Micheli
EPFL, CH
,
Program Chairs:
Bashir Al-Hashimi
University of Southampton, UK
,
Wolfgang Mueller
University of Paderborn, DE

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

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DATE '09

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '09: Design, Automation and Test in Europe

April 20 - 24, 2009

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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DATE '25

Sponsor:
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Design, Automation and Test in Europe

March 31 - April 2, 2025

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Cited By

View all

Sneps-Sneppe MNamiot D(2018)Time to Rethink the Power of Packet SwitchingProceedings of the 23rd Conference of Open Innovations Association FRUCT10.5555/3299905.3299955(369-374)Online publication date: 19-Nov-2018
https://dl.acm.org/doi/10.5555/3299905.3299955
Luo HWei SChen DGuo D(2014)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2014.05.00374:9(2818-2830)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1016/j.jpdc.2014.05.003
Xiao CFrank Chang MCong JGill MHuang ZLiu CReinman GWu H(2013)Stream arbitrationACM Transactions on Architecture and Code Optimization10.1145/2400682.24007199:4(1-27)Online publication date: 20-Jan-2013
https://dl.acm.org/doi/10.1145/2400682.2400719
Matos DReinbrecht CKreutz MPalermo GCarro LSusin A(2013)Hierarchical and multiple switching NoC with floorplan based adaptabilityProceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications10.1007/978-3-642-36812-7_17(179-184)Online publication date: 25-Mar-2013
https://dl.acm.org/doi/10.1007/978-3-642-36812-7_17
Teimouri NModarressi MTavakkol ASarbazi-azad H(2011)Energy-optimized on-chip networks using reconfigurable shortcut pathsProceedings of the 24th international conference on Architecture of computing systems10.5555/1966221.1966248(231-242)Online publication date: 24-Feb-2011
https://dl.acm.org/doi/10.5555/1966221.1966248
Modarressi MSarbazi-Azad HTavakkol ASapatnekar S(2010)An efficient dynamically reconfigurable on-chip network architectureProceedings of the 47th Design Automation Conference10.1145/1837274.1837316(166-169)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837316

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