More Web Proxy on the site http://driver.im/

research-article

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture

Authors:

Henning Sahlbach,

Wolfram Putzke-RömingAuthors Info & Claims

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 27 - 32

Published: 20 April 2009 Publication History

Abstract

Despite recent advances in FPGA, GPU, and general purpose processor technologies, the challenges posed by real-time digital image processing at high resolutions cannot be fully overcome due to insufficient processing capability, inadequate data transport and control mechanisms, and often prohibitively high costs. To address these issues, we proposed a two-phase solution for a real-time film grain noise reduction application. The first phase is based on a state-of-the-art FPGA platform used as a reference design. The second phase is based on a novel heterogeneous reconfigurable computing platform that offers flexibility not available from other computing paradigms. This paper introduces the heterogeneous platform and briefly reviews our previous work with the application in question, as well as its implementation on the FPGA demonstration board during the first phase. Then we present a decomposition of the application, which allows an efficient mapping to the new heterogeneous computing platform through the use of its diverse reconfigurable computing units and run-time reconfiguration.

References

[1]

A. do Carmo Lucas, H. Sahlbach, S. Whitty, S. Heithecker, and R. Ernst, "Application Development with the FlexWAFE Real-time Stream Processing Architecture for FPGAs," ACM Transactions on Embedded Computing Systems, Special Issue on Configuring Algorithms, Processes and Architecture (CAPA), 2009, to appear.

Digital Library

[2]

Nallatech Ltd, "DIMEtalk 3 Product Brief," 2007.

[3]

Hunt Engineering Ltd. Homepage. {Online}. Available: http://www.hunteng.co.uk

[4]

S. Shukla, N. W. Bergmann, and J. Becker, "APEX - A Coarse-Grained Reconfigurable Overlay for FPGAs," in Proceedings of the IFIP VLSI SoC, 2005.

[5]

Thomson. Scream 4K/2K Resolution-Independent Grain Reducer. Thomson Grass Valley. {Online}. Available: http://www.thomsongrassvalley.com

[6]

DaVinci. Homepage. {Online}. Available: http://geniusofdavinci.com

[7]

A. Kumar, A. Hansson, J. Huisken, and H. Corporaal, "An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip," in Proc. Design, Automation & Test in Europe Conference & Exhibition DATE '07, 16--20 April 2007, pp. 1--6.

Digital Library

[8]

K.-B. Lee, T.-C. Lin, and C.-W. Jen, "An Efficient Quality-Aware Memory Controller for Multimedia Platfrom SoC," IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 5, pp. 620--633, May 2005.

Digital Library

[9]

S. Whitty and R. Ernst, "A Bandwidth Optimized SDRAM Controller for the MORPHEUS Reconfigurable Architecture," in Parallel and Distributed Processing Symposium (IPDPS). IEEE, April 2008.

[10]

D. Blythe, "Rise of the Graphics Processor," Proceedings of the IEEE, vol. 96, no. 5, pp. 761--778, May 2008.

[11]

J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, "Introduction to the Cell multiprocessor," in IBM Journal of Research and Development, 2005.

Digital Library

[12]

V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, "PACT XPP---A Self-Reconfigurable Data Processing Architecture," in The Journal of Supercomputing, 2004.

Digital Library

[13]

F. Campi, A. Deledda, M. Pizzotti, L. Ciccarelli, P. Rolandi, C. Mucci, A. Lodi, A. Vitkovski, and L. Vanzolini, "A dynamically adaptive DSP for heterogeneous reconfigurable platforms," in Proceedings of the Conference on Design, Automation and Test in Europe. ACM Press New York, NY, USA, 2007, pp. 9--14.

Digital Library

[14]

Abound Logic. Homepage. {Online}. Available: http://www.aboundlogic.com/index.html

[15]

E. M. Panainte, K. Bertels, and S. Vassiliadis, "The Molen Compiler for Reconfigurable Processors," ACM Transactions in Embedded Computing Systems (TECS), February 2007.

Digital Library

[16]

F. Thoma, M. Kühnle, P. Bonnot, E. M. Panainte, K. Bertels, S. Goller, A. Schneider, S. Guyetant, E. Schüler, K. D. Müller-Glaser, and J. Becker, "MORPHEUS: Heterogeneous Reconfigurable Computing," in Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07), August 2007.

[17]

G. de Haan, P. Biezen, H. Huijgen, and O. A. Ojo, "True motion estimation with 3d recursive search block matching," IEEE Trans. Circuits and Systems for Video Technology, vol. 3, pp. 368--379, October 1993.

Digital Library

[18]

S. Eichner, G. Scheller, U. Wessely, H. Rückert, and R. Hedtke, "Motion compensated spatial-temporal reduction of film grain noise in the wavelet domain," in SMPTE Technical Conference, New York, 2005.

[19]

S. Heithecker, A. do Carmo Lucas, and R. Ernst, "A High-End Real-Time Digital Film Processing Reconfigurable Platform," EURASIP Journal on Embedded Systems, Special Issue on Dynamically Reconfigurable Architectures, vol. 2007, pp. Article ID 85318, 15 Pages, 2007.

Digital Library

[20]

G. Kahn, "The semantics of a simple language for parallel programming," in Information Processing, 1974.

Cited By

Voros NHübner MBecker JKühnle MThomaitiv FGrasset ABrelet PBonnot PCampi FSchüler ESahlbach HWhitty SErnst RBillich ETischendorf CHeinkel UIeromnimon FKritharidis DSchneider AKnaeblein JPutzke-Röming W(2013)MORPHEUSACM Transactions on Embedded Computing Systems10.1145/2442116.244212012:3(1-33)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442120
Rossi DMucci CCampi FSpolzino SVanzolini LSahlbach HWhitty SErnst RPutzke-Röming WGuerrieri R(2013)Application space exploration of a heterogeneous run-time configurable digital signal processorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218596321:2(193-205)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2185963
Whitty SSahlbach HHurlburt BErnst RPutzke-Röming WDe Micheli GAl-Hashimi BMueller WMacii E(2010)Application-specific memory performance of a heterogeneous reconfigurable architectureProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871020(387-392)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871020

Recommendations

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as ...
A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable ...
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

April 2009

1776 pages

ISBN:9783981080155

General Chairs:
Luca Benini
University of Bologna, IT
,
Giovanni De Micheli
EPFL, CH
,
Program Chairs:
Bashir Al-Hashimi
University of Southampton, UK
,
Wolfgang Mueller
University of Paderborn, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

Check for updates

Qualifiers

Research-article

Conference

DATE '09

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '09: Design, Automation and Test in Europe

April 20 - 24, 2009

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
84
Total Downloads

Downloads (Last 12 months)7
Downloads (Last 6 weeks)2

Reflects downloads up to 18 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Voros NHübner MBecker JKühnle MThomaitiv FGrasset ABrelet PBonnot PCampi FSchüler ESahlbach HWhitty SErnst RBillich ETischendorf CHeinkel UIeromnimon FKritharidis DSchneider AKnaeblein JPutzke-Röming W(2013)MORPHEUSACM Transactions on Embedded Computing Systems10.1145/2442116.244212012:3(1-33)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442120
Rossi DMucci CCampi FSpolzino SVanzolini LSahlbach HWhitty SErnst RPutzke-Röming WGuerrieri R(2013)Application space exploration of a heterogeneous run-time configurable digital signal processorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218596321:2(193-205)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2185963
Whitty SSahlbach HHurlburt BErnst RPutzke-Röming WDe Micheli GAl-Hashimi BMueller WMacii E(2010)Application-specific memory performance of a heterogeneous reconfigurable architectureProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871020(387-392)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871020

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents