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Computation of yield-optimized Pareto fronts for analog integrated circuit specifications

Authors:

Daniel Mueller-Gritschneder,

Helmut GraebAuthors Info & Claims

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1088 - 1093

Published: 08 March 2010 Publication History

Abstract

For any analog integrated circuit, a simultaneous analysis of the performance trade-offs and impact of variability can be conducted by computing the Pareto front of the realizable specifications. The resulting Specification Pareto front shows the most ambitious specification combinations for a given minimum parametric yield. Recent Pareto optimization approaches compute a so-called yield-aware specification Pareto front by applying a two-step approach. First, the Pareto front is calculated for nominal conditions. Then, a subsequent analysis of the impact of variability is conducted. In the first part of this work, it is shown that such a two-step approach fails to generate the most ambitious realizable specification bounds for mismatch-sensitive performances. In the second part of this work, a novel single-step approach to compute yield-optimized specification Pareto fronts is presented. Its optimization objectives are the realizable specification bounds themselves. Experimental results show that for mismatch-sensitive performances the resulting yield-optimized specification Pareto front is superior to the yield-aware specification Pareto front.

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Cited By

Statter YChen T(2016)A novel high-throughput method for table look-up based analog design automationIntegration, the VLSI Journal10.1016/j.vlsi.2015.09.00352:C(168-181)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.09.003
Graeb HRosenstiel WMacii E(2012)ITRS 2011 analog EDA challenges and approachesProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492993(1150-1155)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492993

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

March 2010

1868 pages

ISBN:9783981080162

General Chairs:
Giovanni De Micheli
EPF Lausanne, CH
,
Bashir Al-Hashimi
University of Southampton, UK
,
Program Chairs:
Wolfgang Mueller
University of Paderborn, SE
,
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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Research-article

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DATE '10

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '10: Design, Automation and Test in Europe

March 8 - 12, 2010

Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Citations

Cited By

Statter YChen T(2016)A novel high-throughput method for table look-up based analog design automationIntegration, the VLSI Journal10.1016/j.vlsi.2015.09.00352:C(168-181)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.09.003
Graeb HRosenstiel WMacii E(2012)ITRS 2011 analog EDA challenges and approachesProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492993(1150-1155)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492993

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