> module Main
> where

> import Lava
> import Lava.Virtex2

> nandGate :: (Bit, Bit) -> Out Bit
> nandGate = and2 >-> inv

> nandGateCircuit :: Out ()
> nandGateCircuit =
>   do
>     a <- inputPort "a" BitType 
>     b <- inputPort "b" BitType 
>     o <- nandGate (a, b)
>     outputPort "o" BitType o

> main :: IO ()
> main = do let nl = computeNetlist "nandgate" Virtex2 nandGateCircuit
>           putXilinxVHDL nl
>           putXilinxEDIF nl